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12-Bit High Output Current Source ADN8810
FEATURES
High precision 12-bit current source Low noise Long term stability Current output from 0 mA to 300 mA Output fault indication Low drift Programmable maximum current 24-lead 4 mm x 4 mm leadframe chip scale package 3-wire serial interface
FUNCTIONAL BLOCK DIAGRAM
5V 5V 3.3V
ENCOMP RESET 4.096V RESET VREF CS SERIAL INTERFACE SCLK SDI ADDRESS 3 ADDR0-2 FAULT
DVDD
AVDD
PVDD FB RSN 1.6V IOUT RSN 1.6V RSN D1
ADN8810
SB
AVSS DVSS DGND
03195-0-001
APPLICATIONS
Tunable laser current source Programmable high output current source Automatic test equipment
SB FAULT INDICATION
Figure 1.
GENERAL DESCRIPTION
The ADN8810 is a 12-bit current source with an adjustable full-scale output current of up to 300 mA. The full-scale output current is set with two external sense resistors. The output compliance voltage is 2.5 V, even at output currents up to 300 mA. The device is particularly suited for tunable laser control and can drive tunable laser front mirror, back mirror, phase, gain, and amplification sections. A host CPU or microcontroller controls the operation of the ADN8810 over a 3-wire SPI(R) interface. The 3-bit address allows up to eight devices to be independently controlled while attached to the same SPI bus. The ADN8810 is guaranteed with 4 LSB INL and 0.75 LSB DNL. Noise and digital feedthrough are kept low to ensure low jitter operation for laser diode applications. Full-scale and scaled output currents are given in Equations 1 and 2, respectively.
I FS
VREF 10 x RSN
VREF 1 RSN x x + 0.1 4096 RSN 15k
(1)
IOUT = Code x
(2)
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADN8810 TABLE OF CONTENTS
ADN8810-Specifications ................................................................ 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 ADN8810 Terminology ................................................................... 8 Typical Performance Characteristics ............................................. 9 Functional Description .................................................................. 11 Setting Full-Scale Output Current ........................................... 11 Reference Voltage Source .......................................................... 11 Power Supplies ............................................................................ 11 Serial Data Interface................................................................... 11 Standby and Reset Modes ......................................................... 12 Power Dissipation ...................................................................... 12 Using Multiple ADN8810s for Additional Output Current . 12 Adding Dither to the Output Current ..................................... 12 Driving Common-Anode Laser Diodes ................................. 13 PC Board Layout Recommendations ...................................... 13 Suggested Pad Layout for CP-24 Package ............................... 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADN8810 ADN8810-SPECIFICATIONS
Table 1. Electrical Characteristics (AVDD = DVDD = 5 V, PVDD = 3.3 V, AVSS = DVSS = DGND = 0 V, TA= 25C, covering IOUT from 2% IFS to 100% IFS, unless otherwise noted.)
Parameter DC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Offset Offset Drift Gain Error REFERENCE INPUT Reference Input Voltage Input Current Bandwidth ANALOG OUTPUT Output Current Change vs. Output Voltage Change Max Output Current Output Compliance Voltage AC PERFORMANCE Settling Time Bandwidth Current Noise Density @10 kHz Symbol N INL DNL RSN = 1.6 ; IOUT = 127 mA Condition Min Typ 12 4 0.75 8 15 1 4.3 1 Max Unit Bit LSB LSB LSB ppm/C %FS V A MHz ppm/V mA V s MHz nA/Hz nA/Hz nA/Hz s 5.5 5.5 5.5 5 5 50 2 V V V A/V A/V A mA mA mA mA V V V 0.5 1 0.5 0.8 2.4 4 V A V V V V
4
VREF BWREF IOUT/VOUT IMAX VCOMP S BW iN VOUT = 0.7 V to 2.0 V RSN1 = 1.37 -40C to +85C; IFS=300 mA
3.9
4.096 2 100
400
300 2.0
2.5 3 5 7.5 3 1.5 6
IFS = 250 mA IFS = 100 mA IFS= 50 mA
Standby Recovery POWER SUPPLY1 Power Supply Voltage
Power Supply Rejection Ratio Supply Current
DVDD AVDD PVDD PSRR IDVDD IAVDD IPVDD IAVDD IPVDD
3.0 4.5 3.0 AVDD = 4.5 V to 5.5 V; * PVDD = 3.0 V to 3.6 V; * IO = 0 mA, SB = DVDD IO = 0 mA, SB = DVDD IO = 0 mA, SB = DVDD SB = 0 V SB = 0 V
5 5 3.3 0.4 0.4 11 1 3 1 0.33 PVDD - 0.6 AVSS + 0.2
FAULT DETECTION Load Open Threshold Load Short Threshold FAULT Logic Output LOGIC INPUTS Input Leakage Current Input Low Voltage Input High Voltage
VOH VOL IIL VIL VIH
DVDD = 5.0 V DVDD = 5.0 V
4.5
DVDD = 3.0 V DVDD = 5 V DVDD = 3.0 V DVDD = 5 V
Rev. 0 | Page 3 of 16
ADN8810
Parameter INTERFACE TIMING2 Clock Frequency RESET Pulsewidth
NOTES 1 With respect to AVSS. 2 See Timing Characteristics for timing specifications. * RSN = 20
Symbol fCLK t11
Condition
Min
Typ
Max 12.5
Unit MHz ns
40
Rev. 0 | Page 4 of 16
ADN8810 TIMING CHARACTERISTICS1, 2
Table 2. Timing Characteristics
Parameter fCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Description SCLK Frequency SCLK Cycle Time SCLK Width High SCLK Width Low CS Low to SCLK High Setup CS High to SCLK High Setup SCLK High to CS Low Hold SCLK High to CS High Hold Data Setup Data Hold CS High Pulsewidth RESET Pulsewidth CS High to RESET Low Hold Min 80 40 40 15 15 35 20 15 2 30 40 30 Typ Max 12.5 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns
NOTES 1 Guaranteed by design. Not production tested. 2 Sample tested during initial release and after any redesign or process change that may affect these parameters. All input signals are measured with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2.
t1
SCLK
t6 t4
CS
t3
t2
t7
t5
t10 t8 t9
SDI
A3*
A2
A1
A0
D11
D10
D0
t12
RESET * ADDRESS BIT A3 MUST BE LOGIC LOW
t11
03195-0-002
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 16
ADN8810 ABSOLUTE MAXIMUM RATINGS
Table 3. ADN8810 Absolute Maximum Ratings
Parameter Supply Voltage Input Voltage Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range CP Package Lead Temperature Range (Soldering 10 sec) Rating 6V GND to VS+ 0.3 V Indefinite -65C to +150C -40C to +85C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 16
ADN8810 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESET DGND DVDD SCLK SDI CS
24 23
22 21 20 19 18
ADDR2 1 RSN 2 FB 3 ADDR1 4 ADDR0 5 FAULT 6
7 8 9 10 11 12 PIN 1 IDENTIFIER
DVSS NC AVSS AVDD VREF NC
17 16 15 14 13
ADN8810
TOP VIEW
(Not to Scale)
SB
IOUT
IOUT
ENCOMP
PVDD
PVDD
NC = NO CONNECT
Figure 3. Pin Configuration
Table 4. Pin Function Description
Pin No. 1 2 3 4 5 6 7 8, 11 9, 10 12 13 14 15 16 17 18 19 20 21 22 23 24 Mnemonic ADDR2 RSN FB ADDR1 ADDR0 FAULT SB PVDD IOUT ENCOMP NC VREF AVDD AVSS NC DVSS SDI SCLK CS RESET DVDD DGND Type Digital Input Analog Input Analog Input Digital Input Digital Input Digital Output Digital Input Power Analog Output Digital Input Analog Input Power Ground Ground Digital Input Digital Input Digital Input Digital Input Power Ground Description Chip Address, Bit 2 Sense Resistor RS2 Feedback Sense Resistor RS1 Feedback Chip Address, Bit 1 Chip Address, Bit 0 Load Open/Short Indication Active Deactivates Output Stage (High Output Impedance State) Power Supply for IOUT (3.3 V Recommended) Current Output Connect to AVSS No Connection Input for High Accuracy External Reference Voltage (ADR292ER) Power Supply for DAC Connect to Analog Ground or Most Negative Potential in Dual-Supply Applications No Connection Connect to Digital Ground or Most Negative Potential in Dual-Supply Applications Serial Data Input Serial Clock Input Chip Select; Active Low Asynchronous Reset to Return DAC Output to Code Zero; Active Low Power Supply for Digital Interface Digital Ground
Rev. 0 | Page 7 of 16
03195-0-003
ADN8810 ADN8810 TERMINOLOGY
Relative Accuracy Compliance Voltage
Relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in least significant bits (LSBs), from an ideal line passing through the endpoints of the DAC transfer function. Figure 5 shows a typical INL vs. code plot. The ADN8810 INL is measured from 2% to 100% of the full-scale (FS) output.
Differential Nonlinearity
The maximum output voltage from the ADN8810 is a function of output current and supply voltage. Compliance voltage defines the maximum output voltage at a given current and supply voltage to guarantee the device operates within its INL, DNL, and gain error specifications.
Output Current Change vs. Output Voltage Change
Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. The ADN8810 is guaranteed monotonic by design. Figure 6 shows a typical DNL vs. code plot.
Offset Error
This is a measure of the ADN8810 output impedance and is similar to a load regulation spec in voltage references. For a given code, the output current changes slightly as output voltage increases. It is measured as an absolute value in (ppm of fullscale range)/V.
GAIN ERROR PLUS OFFSET ERROR INTERPOLATED
OUTPUT VOLTAGE
Offset error, or zero-code error, is an interpolation of the output voltage at code 0x000 as predicted by the line formed from the output voltages at code 0x040 (2% FS) and code 0xFFF (100% FS). Ideally, the offset error should be 0 V. Offset error occurs from a combination of the offset voltage of the amplifier and offset errors in the DAC. It is expressed in LSBs.
Offset Drift
IDEAL
This is a measure of the change in offset error with a change in temperature. It is expressed in (ppm of full-scale range)/C.
Gain Error
ACTUAL (EXAGGERATED)
Gain error is a measure of the span error of the DAC. It is the deviation in slope of the output transfer characteristic from ideal. The transfer characteristic is the line formed from the output voltages at code 0x040 (2% FS) and code 0xFFF (100% FS). It is expressed as a percent of the full-scale range.
Figure 4. Output Transfer Function
Rev. 0 | Page 8 of 16
03195-0-004
OFFSET ERROR
0x040 DAC CODE
0xFFF
ADN8810 TYPICAL PERFORMANCE CHARACTERISTICS
1.2 1.0 0.8 0.10 0.20 0.15
INL ERROR (LSB)
0.6 0.4 0.2 0 -0.2 -0.10 -0.4
03195-0-005
DNL (LSB)
0.05 0 -0.05
-0.6 -0.8 0 500
-0.15 -0.20 -40
1,000 1,500 2,000 2,500 3,000 3,500 4,000 4,500 CODE
-15
10 35 TEMPERATURE (C)
60
85
Figure 5. Typical INL Plot
0.4 0.3
Figure 8. DNL vs. Temperature
0.258 RS = 1.6 0.257
FULL-SCALE OUTPUT (A)
0.2
0.256 0.255 0.254 0.253 0.252 0.251 0.250 -40
03195-0-009
DNL ERROR (LSB)
0.1
0 -0.1 -0.2
-0.3
0
500
1,000 1,500 2,000 2,500 3,000 3,500 4,000 4,500 CODE
03195-0-006
-15
10 35 TEMPERATURE (C)
60
85
Figure 6. Typical DNL Plot
0.20 0.15 0.10 0.05 0 -0.05 -0.10
03195-0-007
Figure 9. Full-Scale Output vs. Temperature
20.765 RS = 20 20.760
FULL-SCALE OUTPUT (mA)
20.755 20.750 20.745 20.740 20.735 20.730 20.725 20.720 -40
03195-0-010
DINL (LSB)
-0.15 -0.20 -40
-15
10 35 TEMPERATURE (C)
60
85
-15
10 35 TEMPERATURE (C)
60
Figure 7. INL vs. Temperature
Figure 10. Full-Scale Output vs. Temperature
Rev. 0 | Page 9 of 16
03195-0-008
85
ADN8810
0.50 0.45 0.40 0.35 IPVDD (mA) 0.30 0.25 0.20 0.15 0.10
03195-0-011
CODE = x000
105 RS = 1.6 104
OUTPUT IMPEDANCE ()
103
102
101
03195-0-014
0.05 0 -40 -15 10 35 TEMPERATURE (C) 60
85
10 10 100 1k 10k FREQUENCY (Hz) 100k
1M
Figure 11. PVDD Supply Current vs. Temperature
12 CODE = x000
0 0
Figure 14. Output Impedance vs. Frequency
CODE: x700 TO xFFF 5V/DIV CS 0
10
8
VOLTA (2.7V/DIV) GE
0 0 0 0
IDVDD (A )
6
4
03195-0-012
IOUT 0 0 0 0 000 0 0 TIME (1s/DIV) 0 0 0
0 -40
-15
10
35
60
85
TEMPERATURE (C)
Figure 12. DVDD Supply Current vs. Temperature
1.5 CODE = x000 1.4 CS
Figure 15. Full-Scale Settling Time
CODE: x7FF TO x800 RS = 1.6 5V/DIV
IAVDD (mA)
1.3
1.2
IOUT 10mA/DIV
03195-0-013
1.0 -40
0
0
0
-15
10 35 TEMPERATURE (C)
60
85
000 0 0 TIME (200ns/DIV)
0
0
0
Figure 13. AVDD Supply Current vs. Temperature
Figure 16. 1 LSB Settling Time
Rev. 0 | Page 10 of 16
03195-0-016
1.1
03195-0-015
2
300mA/DIV
ADN8810 FUNCTIONAL DESCRIPTION
The ADN8810 is a single 12-bit current output D/A converter with a 3-wire SPI interface. Up to eight devices can be independently programmed from the same SPI bus. The full-scale output current is set with two external resistors. The maximum output current can reach 300 mA. Figure 17 shows the functional block diagram of the ADN8810.
*
AVDD provides power to the analog front end of the ADN8810 including the DAC. Use this supply line to power the external voltage reference. For best performance, AVDD should be low noise. DVDD provides power for the digital circuitry. This includes the serial interface logic, the SB and RESET logic inputs, and the FAULT output. Tie DVDD to the same supply line used for other digital circuitry. It is not necessary for DVDD to be low noise. PVDD is the power pin for the output amplifier. It can operate from as low as 3.0 V to minimize power dissipation in the ADN8810. For best performance, PVDD should be low noise.
*
DVDD AVDD FAULT
FB
ENCMP
SB
BIAS GEN
FAULT DETECTION 1.5k PVDD PVDD 12-BIT DAC IOUT IOUT
*
VREF
Current is returned through three pins:
*
03195-0-017
CS SCLK SDI CONTROL LOGIC
12-BIT DATA LATCH ADDRESS DECODER
AVSS 1.5k RSN 15k
DGND
ADDR2 ADDR1 ADDR0 RESET
DVSS
AVSS is the return path for both AVDD and PVDD. This pin is connected to the substrate of the die as well as the slug on the bottom of the LFCSP package. For singlesupply operation, this pin should be connected to a low noise ground plane. DVSS returns current from the digital circuitry powered by DVDD. Connect DVSS to the same ground line or plane used for other digital devices in the application. DGND is the ground reference for the digital circuitry. In a single-supply application, connect DGND to DVSS.
Figure 17. Functional Block Diagram
SETTING FULL-SCALE OUTPUT CURRENT
Two external resistors set the full-scale output current from the ADN8810. These resistors are equal in value and are labeled RSN in the Functional Block Diagram on the front page. Use 1% or better tolerance resistors to achieve the most accurate output current and the highest output impedance. Equation 1 shows the approximate full-scale output current. The exact output current is determined by the data register code as shown in Equation 2. The variable code is an integer from 0 to 4095, representing the full 12-bit range of the ADN8810. I FS 4.096 10 x RSN
Code 1 RSN x x + 0.1 1,000 RSN 15k
*
*
For single-supply operation, set AVDD to 5 V, set PVDD from 3.0 V to 5 V, and connect AVSS, AGND, and DGND to ground.
SERIAL DATA INTERFACE
The ADN8810 uses a serial peripheral interface (SPI) with three input signals: SDI, CLK, and CS. Figure 2 shows the timing diagram for these signals. Data applied to the SDI pin is clocked into the input shift register on the rising edge of CLK. After all 16 bits of the dataword have been clocked into the input shift register, a logic high on CS loads the shift register byte into the ADN8810. If more than 16 bits of data are clocked into the shift register before CS goes high, bits will be pushed out of the register in first-in firstout (FIFO) fashion. The four most significant bits (MSB) of the data byte are checked against the device's address. If they match, the next 12 bits of the data byte are loaded into the DAC to set the output current. The first bit (MSB) of the data byte must be a logic zero, and the following three bits must correspond to the logic levels on pins ADDR2, ADDR1, and ADDR0, respectively, for the
(1)
IOUT =
(2)
REFERENCE VOLTAGE SOURCE
The ADN8810 is designed to operate with a 4.096 V reference voltage connected to VREF. The output current is directly proportional to this reference voltage. A low noise precision reference should be used to achieve the best performance. The ADR292, ADR392, or REF198 is recommended.
POWER SUPPLIES
There are three principal supply current paths through the ADN8810:
Rev. 0 | Page 11 of 16
ADN8810
DAC to be updated. Up to eight ADN8810 devices with unique addresses can be driven from the same serial data bus. Table 5 shows how the 16-bit DATA input word is divided into an address byte and a data byte. The first four bits in the input Table 5. Serial Data Input Examples
SDI Input Ex. 1 Ex. 2 Ex. 3 Address Byte A3 A2 0 1 0 0 0 1 A1 1 0 0 A0 1 0 0 Data Byte D11 D10 0 0 1 0 1 1 D9 0 0 1
word correspond to the address. Note that the first bit loaded (A3) must always be zero. The remaining bits set the 12-bit data byte for the DAC output. Three example inputs are demonstrated.
D8 0 0 1
D7 0 0 1
D6 0 0 1
D5 0 0 1
D4 0 0 1
D3 0 0 1
D2 0 0 1
D1 0 0 1
D0 0 0 1
Example 1: This SDI input sets the device with an address of 111 to its minimum output current, 0 A. Connecting the ADN8810 pins ADDR2, ADDR1, and ADDR0 to VDD sets this address. Example 2: This input sets the device with an address of 000 to a current equal to half of the full-scale output. Example 3: The ADN8810 with an address of 100 is set to fullscale output.
Example 4: A 300 mA full-scale output current is required to drive a laser diode within an 85C environment. The laser diode has a 2 V drop and PVDD is 3.3 V.
Using Equation 3, the power dissipation in the ADN8810 is found to be 267 mW. At TA = 85C, this makes the junction temperature 93.5C, which is well below the 150C limit. Note that even with PVDD set to 5 V, the junction temperature would increase to only 110C.
STANDBY AND RESET MODES
Applying a logic low to the SB pin deactivates the ADN8810 and puts the output into a high impedance state. The device continues to draw 1.3 mA of typical supply current in standby. Once logic high is reasserted on the SB pin, the output current returns to its previous value within 6 s. Applying logic low to RESET will set the ADN8810 data register to all zeros, bringing the output current to 0 A. Once RESET is deasserted, the data register can be reloaded. Data cannot be loaded into the device while it is in Standby or Reset mode.
USING MULTIPLE ADN8810S FOR ADDITIONAL OUTPUT CURRENT
Connect multiple ADN8810 devices in parallel to increase the available output current. Each device can deliver up to 300 mA of current. To program all parallel devices simultaneously, set all device addresses to the same address byte and drive all CS, SDI, and CLK from the same serial data interface bus. The circuit in Figure 18 uses two ADN8810 devices and delivers 600 mA to the pump laser.
CS SERIAL INTERFACE (FROM C OR DSP) SCLK FB IOUT RS 1.37 RS 1.37 RSN
POWER DISSIPATION
The power dissipation of the ADN8810 is equal to the output current multiplied by the voltage drop from PVDD to the output.
ADN8810
SDI ADDR2 ADDR1 ADDR0
PDISS = I OUT x (PVDD - VOUT ) - I OUT x RS
(3)
CS SCLK
FB IOUT RS 1.37 RS 1.37 RSN D1 ILD 600mA
03195-0-018
The power dissipated by the ADN8810 will cause a temperature increase in the device. For this reason, PVDD should be as low as possible to minimize power dissipation. While in operation, the ADN8810 die temperature, also known as junction temperature, must remain below 150C to prevent damage. The junction temperature is approximately TJ = TA + JA x PDISS where TA is the ambient temperature in C, and JA is the thermal resistance of the package (32C/W). (4)
ADN8810
SDI ADDR2 ADDR1 ADDR0
Figure 18. Using Multiple Devices for Additional Output Current
ADDING DITHER TO THE OUTPUT CURRENT
Some tunable laser applications require the laser diode bias current to be modulated or dithered. This is accomplished by dithering the VREF voltage input to the ADN8810. Figure 19 demonstrates one method.
Rev. 0 | Page 12 of 16
ADN8810
R2 1.62k 5V TO VREF
03195-0-019
pins. Figure shows a simple method to level shift a standard TTL or CMOS (0 V to 5 V) signal down using external FETs.
5V 5V D1 ENCOMP DVDD AVDD PVDD VREF RESET CS SCLK FB IOUT FDC633N OR EQUIV RSN NC I = 300mA @ CODE 0x7F
C 1F DITHER
R1 1.62k
ADR292
5V VIN VOUT GND
4.096V
AD8605
Figure 19. Adding Dither to the Reference Voltage
ADN8810
Set the gain of the dither by adjusting the ratio of R2 to R1. Increase C to lower the cutoff frequency of the high-pass filter created by C and R1. The cutoff frequency of Figure 19 is approximately 10 Hz. The AD8605 is recommended as a low offset, rail-to-rail input amplifier for this circuit.
TTL/CMOS LOGIC LEVELS
3
SDI ADDR0-2 SB
AVSS DVSS DGND
RS 6.81
03195-0-020
NOTE: LEAVE FB WITH NO CONNECTION
DRIVING COMMON-ANODE LASER DIODES
The ADN8810 can power common-anode laser diodes. These are laser diodes whose anodes are fixed to the laser module case. The module case is typically tied to either VDD or ground. For common-anode-to-ground applications, a negative 5 V supply must be provided. In Figure 20, RS sets up the diode current by the equation
1 1 Code I = 4.096 x 1.1 R + 16.5k x 4096 S
Figure 20. Driving Common-Anode-to-VDD Laser Diodes
-5V D1 ENCOMP DVDD AVDD PVDD VREF RESET CS -5V SCLK SDI 3 ADDR0-2 SB AVSS DVSS DGND RS 6.81
03195-0-021
ADR292
VIN VOUT GND
FB IOUT
NC
I = 300mA @ CODE 0x7F
ADN8810
FDC633N OR EQUIV RSN
-5 TO 0V LOGIC LEVELS
(5)
where Code is an integer value from 0 to 4,095. Using the values in Figure 20, the diode current is 300.7 mA at a code value of 2,045 (0x7FF), or one-half full-scale. This effectively provides 11-bit current control from 0 mA to 300 mA of diode current. The maximum output current of this configuration is limited by the compliance voltage at the IOUT pin of the ADN8810. The voltage at IOUT cannot exceed 1 V below PVDD, in this case 4 V. The IOUT voltage is equal to the voltage drop across RS plus the gate-to-source voltage of the external FET. For this reason, select a FET with a low threshold voltage. In addition, the voltage across the RS resistor cannot exceed the voltage at the cathode of the laser diode. Given a forward laser diode voltage drop of 2 V in Figure 20, the voltage at the RSN pin (I x RS) cannot exceed 3 V. This sets an upper limit to the value of Code in Equation 5. Although the configuration for anode-to-ground diodes is similar, the supply voltages must be shifted down to 0 V and -5 V, as shown in Figure. The AVDD, DVDD, and PVDD pins are connected to ground with AVSS connected to -5 V. The 4.096 V reference must also be referred to the -5 V supply voltage. The diode current is still determined by Equation 5. All logic levels must be shifted down to 0 V and -5 V levels as well. This includes RESET, CS, SCLK, SDI, SB, and all ADDR
-5V
-5V
NOTE: LEAVE FB WITH NO CONNECTION
Figure 21. Driving Common-Anode-to-Ground Laser Diodes with a Negative Supply
+3V
100k TTL/CMOS LEVEL NDC7003P OR EQUIV NDC7002N OR EQUIV 10k -5V -5V TO: RESET CS SCLK SDI
03195-0-021
Figure 22. Level Shifting TTL/CMOS Logic
PC BOARD LAYOUT RECOMMENDATIONS
Although they can be driven from the same power supply voltage, keep DVDD and AVDD current paths separate on the PC board to maintain the highest accuracy; likewise for AVSS and DGND. Tie common potentials together at a single point located near the power regulator. This technique is known as star grounding and is shown in Figure. This method reduces digital crosstalk into the laser diode or load.
Rev. 0 | Page 13 of 16
ADN8810
POWER SUPPLY 5V TO OTHER 5V DIGITAL LOGIC LOGIC GROUND RETURN DVDD AVDD PVDD DVSS AVSS DGND IOUT LOAD GND 3V GND
SUGGESTED PAD LAYOUT FOR CP-24 PACKAGE
shows the dimensions for the PC board pad layout for the ADN8810. The package is a 4 mm x 4 mm, 24-lead LFCSP. The metallic slug underneath the package should be soldered to a copper pad connected to AVSS, the lowest supply voltage to the ADN8810. For single-supply applications, this is ground. Use multiple vias to this pad to improve the thermal dissipation of the package.
0.027 (0.69)
ADN8810
Figure 23. Star Supply and Ground Technique
To improve thermal dissipation, the slug on the bottom of the LFCSP package should be soldered to the PC board with multiple vias into a low noise ground plane. Connecting these vias to a copper area on the bottom side of the board will further improve thermal dissipation. Use identical trace lengths for the two output sense resistors. These lengths are shown as X and Y in Figure 24. Differences in trace lengths cause differences in parasitic series resistance. Because the sense resistors can be as low as 1.37 , small parasitic differences can lower both the output current accuracy and the output impedance. Application Note AN-619 shows a good layout for these traces.
ADN8810
FB X RSN IOUT RSN Y RSN TO LOAD
03195-0-024
03195-0-023
LOAD
0.004 (0.10)
0.011 (0.28)
0.172 (4.36)
0.109 (2.78)
0.020 (0.50)
PACKAGE OUTLINE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
Figure 25. Suggested PC Board Layout for CP-24 Pad Landing
Figure 24. Use Identical Trace Lengths for Sense Resistors
Rev. 0 | Page 14 of 16
03195-0-025
DIMENSIONS ARE SHOWN IN INCHES AND (MM).
0.106 (2.68)
ADN8810 OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX 0.60 MAX
19 18 24 1
PIN 1 INDICATOR 2.25 2.10 SQ 1.95
6
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
BOTTOM VIEW
13 12 7
0.25 MIN 2.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 26. 24-Lead Lead Frame Chip Scale Package [LFCSP] (CP-24) Dimensions shown in millimeters
ORDERING GUIDE
Model ADN8810ACP ADN8810ACP- REEL7 ADN8810-EVAL Temperature Range -40C to +85C -40C to +85C Package Description 24-Lead LFCSP 24-Lead LFCSP Evaluation Board Package Option CP-24 CP-24
Rev. 0 | Page 15 of 16
ADN8810 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03195-0-1/04(0)
Rev. 0 | Page 16 of 16

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